Status Register
| TFE | Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. |
| TNF | Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. |
| RNE | Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. |
| RFF | Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. |
| BSY | Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |